The present invention relates generally to a semiconductor device and a process for producing the same, and more particularly, to a semiconductor device having bonding pads and a process for producing the same.
When a semiconductor chip is mounted on a ceramic or resin package, the semiconductor chip is subjected to bonding treatment to electrically connect bonding pads on the chip to external lead terminals of the package. Such bonding methods include wire bonding for connecting bonding pads and lead terminals with thin metallic bonding wires and wireless bonding for connecting the bonding pads and the lead terminals without employing bonding wires.
FIG. 1 is a schematic cross-sectional view showing a prior art semiconductor chip 101. The semiconductor chip 101 comprises MOS transistors 103 formed on a semiconductor substrate 102 and a multilayer wiring 104 also formed on the semiconductor substrate 102.
The MOS transistors 103 each comprise source/drain regions 105 and a gate electrode 106. The source/drain regions 105 are formed on the semiconductor substrate 102. The gate electrode 106 is formed on the semiconductor substrate 102 between the source/drain regions 105 via a gate insulating film 107.
The multilayer wiring 104 comprises layer insulating films 108 and 109, a device-isolating insulating film 110, wirings 111 and 112, bonding pads 113, via holes 114 and 115, plugs 116 and 117 embedded in the via holes 114 and 115 respectively, and a passivation film 118.
The device-isolating insulating film 110 is formed on the semiconductor substrate 102 to isolate devices such as the MOS transistors 103 from one another. The layer insulating film 108 is formed on the semiconductor substrate 102 and on the device-isolating insulating film 110. The wirings 111 are formed on the layer insulating film 108. The wirings 112 are formed on the layer insulating film 109 which is the uppermost layer. Each bonding pad 113 is formed on the layer insulating film 109 using the same material and in the same step as the wirings 112.
The surfaces of the layer insulating films 108 and 109 are flattened by means of CMP (chemical Mechanical Polishing).
The layer insulating film 108 includes a plurality of via holes 114 extending perpendicular to the substrate 102. The plug 116 is embedded in each via hole 114 to connect electrically the source/drain region 105 and the wirings 111. The layer insulating film 109 includes a plurality of via holes 115 extending perpendicular to the substrate 102. The plugs 117 are embedded in the via holes 115 to secure electrical continuity between the wirings 111 and the wirings 112, and between the wirings 111 and the bonding pads 113.
The passivation film 118 is formed on the surface of the semiconductor chip 101 (on the wirings 112 and the layer insulating film 109) except for the central area of each bonding pad 113. The passivation film 118 protects the surface of the semiconductor chip 101 from being scratched or damaged. In other words, the passivation film 118 protects the chip 101. The passivation film 118 also prevents moisture and contaminants from intruding into the devices such as MOS transistors 103 and into the wirings 111 and 112 and plugs 116 and 117.
A bonding wire 119 is connected to the bonding pad 113 at an exposed central surface area (having no passivation film 118 formed thereon) by means of thermocompression bonding. The bonding wire 119 electrically connects the bonding pad 113 to a lead terminal (not shown) of the package.
With higher integration of semiconductor chips 101, wirings 112 are becoming finer to allow for higher wiring densities. The passivation film 118 is becoming thinner at steps in the wirings 112 (around the lower part 112a of each wiring 112) compared with other surface areas of the chip 101. This causes deterioration of the functions of the passivation film 118, disadvantageously. Further, the passivation film 118 can form voids 125, in gaps present between wirings 112. Moisture and contaminants, which affect the semiconductor chip 101, can be confined in the voids 125.
A second prior art semiconductor chip 201 is shown in FIG. 2. The chip 201 has an insulating film 120 formed on the wirings 112 and on the layer insulating film 109. A flattening insulating film 121, such as an SOG (Spin On Glass) film, is formed on the insulating film 120. A passivation film 118 is formed on the flattening insulating film 121. The surface of the passivation film 118 is flattened to have a uniform thickness.
It should be noted here that the central surface area of the bonding pad 113 is exposed through an opening 122 formed through the films 118, 121 and 120. A bonding wire 119 is connected to the central surface area by means of thermocompression bonding.
However, the flattening insulating film 121 exposes itself at the wall of the opening 122. It is known that SOG films have low barrier properties against moisture and contaminants. Accordingly, as arrows "A" indicate in FIG. 2, moisture and contaminants may creep along the wall of the opening 122 and penetrate the flattening insulating film 121, thereby contaminating the semiconductor chip 201. The moisture and contaminants which intrude into the chip 201 causes deterioration of the properties of devices, such as MOS transistors 103 and continuity failure due to corrosion in the wirings 111 and 112 and plugs 116 and 117, thereby lowering wiring reliability.
It is an objective of the present invention to provide a semiconductor device having bonding pads which prevent deterioration of device performance and wiring reliability, as well as, a process for producing the same.